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SPLD, EEPLD, 20 ns, 10 I/O's, 50 MHz, 80 mA, DIP, 24 Pins

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Inkl. moms:
Kr. 47,50
v/5Kr. 43,75
v/15Kr. 37,50
v/100Kr. 28,75
v/1000Kr. 22,50
  • Industry-standard architecture
  • 12ns Maximum pin-to-pin delay
  • Zero power - 100µA maximum standby power (input transition detection)
  • CMOS and TTL compatible inputs and outputs
  • Advanced electrically erasable technology - Reprogrammable, 100% tested
  • Latch feature holds inputs to previous logic state
  • High-reliability CMOS process
  • 20 years Data retention
  • 100 Erase/write cycles
  • 2,000V ESD protection
  • 200mA Latch-up immunity
  • Industrial temperature range
  • PCI compliant
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